The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including an interconnect dielectric material layer containing an embedded copper or copper alloy in which an upper portion of the copper or copper alloy has been modified to mitigate or prevent preferential loss of copper. The modified upper portion of the copper or copper alloy, which is formed in part by ion implantation of a dopant metal, can aid in lowering the interconnect resistance of the structure.
Aggressive scaling has exposed limitations of extending the conventional copper plating process to advanced technology nodes. Dissolution of copper seed layers in the electroplating bath and sidewall voiding are some of the challenges with the conventional approach. Introduction of a thin ruthenium reflow enhancement layer has helped to mitigate these challenges and enables a plating-based or high temperature physical vapor deposition copper approach for interconnect metallization.
However, during the planarization of the ruthenium enhancement layer by chemical mechanical polishing (CMP), preferential loss of significant amounts of copper is observed and has been attributed to galvanic corrosion. This leads to a significant increase in the interconnect line and via resistance. As such, there is a need for providing a structure and a method to mitigate or prevent preferential loss of copper which can help lower the interconnect resistance.